The present invention relates to a semiconductor memory and more particularly to a dynamic type semiconductor memory device.
Dynamic type memories have been widely utilized in variety of fields as large capacity memories.
Typical structure of a dynamic memory is such that a plurality of dynamic memory cells are arranged in rows and columns with word lines in rows and a plurality pairs of bit lines in columns. A sense amplifier is disposed at one end of a pair of bit lines and connected thereto. Upon selection of one of word lines, a memory cell connected to the selected word line produces a stored signal to one of the pair of bit lines connected thereto. The sense amplifier operatively amplifies a difference in potentials between the above pair of bit lines. Then, a selected one of the sense amplifiers is electrically connected to a pair of bus lines via a selected pair of column switch transistors thereby to transfer the amplified read signal to the pair of bus lines.
The above-described type of conventional semiconductor memory device suffers, however, from the problem that, if it is intended to increase the integration density, the number of memory cells which are connected to each bit line increases, which causes an increase in the length of the bit line, resulting in an increase in the parasitic capacitance and hence a lowering in the level of sensitivity of the sense amplifier.
To cope with the above-described problem, a method wherein each bit line pair is divided into a multiplicity of sections to thereby reduce the parasitic capacitance has been proposed. However, if the bit line pair is divided into a multiplicity of sections, it is necessary to increase the number of column switch transistors which are required to connect the sections to the bus lines, and an increase in the number of column switch transistors causes an increase in the parasitic capacitance of the bus lines. For this reason, all the sense amplifiers are required not only to amplify the difference in potentials between the respective pairs of bit lines but also to further amplify the read signal in order to drive the bus lines, and it is also necessary to increase the number of sense amplifiers in accordance with the division of each bit line pair into a multiplicity of sections, which results, disadvantageously, in a substantial increase in the power consumption.
Furthermore, due to the large capacitance of the bus lines, it is difficult to drive the bus lines by the selected sense amplifier at a high speed.